Posts

Showing posts from November, 2017

cGMP AUDITS AND COMPLIANCE

Image
Facts about the cGMP AUDITS AND COMPLIANCE ? cGMP stands for Current Good Manufacturing Practice regulation enforced by the US Food and Drug Administration (FDA). India has become a priority location for the USFDA as it houses the largest number of FDA-approved drug manufacturing plants outside the US. India with its Rs.1.1 trillion drug industry, which largely makes generics, exported around Rs.50,000 crore of drugs in 2016-2017.   USFDA has increased the number of inspections at FDA approved units. The number of FDA 483 and warning letters,import alerts issued to pharmaceutical companies globally, have risen over the years and have been asked to review and strengthen its CAPA (Corrective Action Preventive Action) practices.           Why Audits observation CAPA ?   CAPA: CAPA stand for Corrective and Preventive Action. FDA and regulatory agencies are looking closely in how Pharmaceutical companies conduct their investigations, and CAPA is viewed as the ce

FUNCTIONAL SAFETY AS PER IEC 61511 SIF SIS SIL TRAINING

Image
SAFETY INSTRUMENTED SYSTEMS SIS SAFETY INTEGRITY LEVEL SIL AS PER IEC 61511 Course Description FUNCTIONAL SAFETY COURSE OBJECTIVES: The main objective of this training program is to give engineers involved in safety instrumented systems the opportunity to learn about functional safety, current applicable safety standards (IEC 61511) and their requirements. The Participants will be able to learn to follow:      Understand the basic requirements of the functional safety standards (IEC 61511)         The meaning of SIS, SIF, SIL and other functional safety terminology           Differentiate between safety functions and control functions         The role of Hazard and Risk analysis in setting SIL targets·    Create basic designs of safety instrumented systems considering architectural constraints          Different type of failures and best practices for minimizing them       Understand the effect of redundancy, diagnostics, proof test intervals, hardware faul